A 3D integrated circuit (IC) in the prior art is described as a system-level architecture which comprises a plurality of chips, and each chip comprises a stack structure of a plurality of planar device layers. These chips are interconnected by at least one through-silicon via (TSV) in the Z direction. With the application of 3D technology, TSVs will be scaled down in sizes, the silicon layer will become thinner continuously, and 3D integrated circuits will be applied more extensively.
In some processes for manufacturing 3D integrated circuits, for example, in the process for forming TSVs, conductive materials, such as copper, aluminum, wolfram, or the like, are filled to form TSVs, which will bring about severe thermal-mechanical stress, thereby leading to cracks in the TSVs and in the semiconductor structures surrounding the TSVs, and causing device failure due to variation of current, and the like.